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3.4 - Active-HDL™ 3rd Party Flows: Simulation and Debugging with Xilinx Vivado
3.3 - Active-HDL™ 3rd Party Flows: Simulation & Debugging with Intel Quartus Prime Pro
4.1 - Active-HDL™ Debugging: Introduction to Debugging
2.3 - Active-HDL™ Design Entry: HDL Editor
2.7 - Active-HDL™ Debugging: Code Coverage
2.9 - Active-HDL™ Debugging: Toggle Coverage
2.4 - Active-HDL™ Debugging: Waveform Viewer
3.2 - Active-HDL™ Compilation and Simulation: Compiling Vivado Simulation Libraries
4.2 - Active-HDL™ Debugging: Advance Dataflow
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Last Updated: October 14, 2026
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Summary
Microchip's Libero SoC allows the usage of 3rd party simulators. Because of that, The Signal Agent is a Verilog task or Xilinx Vivado allows the ability to utilize different simulators besides their own. Because of that, the capabilities of Intel Quartus Prime Pro's environment allows for the usage of 3rd party simulators through .tcl and .do scripts. Because of this, one ... Toggle Coverage is a type of Code Coverage in When you instantiate any Xilinx black box component in your design, Advanced Dataflow allows designers to explore the connectivity of an