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Lecture 17: Warp Scheduling and Divergence (Contd.)
Lecture 45: Outperforming cuBLAS on H100
Lecture 18: Warp Scheduling and Divergence (Contd.)
Lecture 87: Low Latency Communication Kernels with NVSHMEM
CUDA Part F: Kernel Optimizations: Shared Memory Accesses; Peter Messmer (NVIDIA)
Acceleration of CUDA Kernels through Fusion Measurements for AvgPool2D and ReLU
Optimized Reduction Kernel Explained | CUDA Warp and Block Reduction
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Last Updated: October 16, 2026
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Summary
Comparator, Sorting subproblem, Bitonic Sort Parallel Implementation. Sorting, Sorting Networks, Bitonic Sort Serial Implementation, Recursion. Sorting bitinic sequence, All Prefix Sum , Inclusive and exclusive scan. Steel inclusive scan, Prefix Sum Implementation, Blelloch Scan Algorithm and Implementation. Control Flow Divergence, Branch Synchronization Stack, Predicated Instructoins. Speaker: Prajwal Singhania High-performance inference at scale is increasingly bottlenecked by communication, especially in ... Programming for GPUs Course: Introduction to OpenACC 2.0 vesves CUDA 5.5 - ember 4-6, 2017. Programming for GPUs ...
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